Bxdty

Starting with the 4116, RAM chips from the late seventies supported fast page mode, where if you were reading nearby – particularly, successive – words, you didn't need to supply both row and column address each time, making second and subsequent words much faster to access. This was used to good effect by some machines, e.g. the video circuitry in the ZX Spectrum.

It seems to me that logically this should also apply to ROM, and would have been useful for some purposes; even if off-the-shelf CPUs of the seventies and eighties didn't have the ability to take advantage of it, at least it could've been used for fetching bitmaps for cartridge games. But I haven't seen it mentioned at all, and Google doesn't seem to have heard of the notion.

Does fast page mode apply to ROM? If so, did any historical machines use it? If not, why not?

Does fast page mode apply to ROM?

No. Why should they?

You're missing one step to start with in your chain of thoughts. (Fast) Page Mode is an improvement to the address multiplex protocol dynamic RAM uses. As such it isn't a general improvement, but a relative one, reducing the overhead the address multiplexing implies.

Address multiplexing was introduced to dynamic RAM by means of the internal organisation needed to handle its RAM cells content (see below for a detailed discussion). Even with the improvement of Page Mode it still suffers from access penalty compared to non multiplexed access.

ROM (and SRAM) did never went that way, as neither needs to use multiplexed addressing, but 'flat' addressing - and wide data words. Adding it would mean to further break down the speed of already slow ROM devices. Not anything system designers desire.

Why do DRAM use address multiplexing?

DRAM needs to refresh its content in cyclic manner. For a 4 KiBit RAM, this would mean 4096 refresh cycles within the data retention time. A typical guaranteed retention time for a 1973 DRAM, like the MK4096, is 2 ms. With a cell based addressing (12 bit 'flat' address) and a cycle time of 500 ns (MK4096-11), 102% of all cycles would need to be refresh cycles, effectively leaving no space for data access while at the same time violating the specifications.

To reduce number of refresh cycles needed, not a single cell is read during a read/refresh cycle, but a whole line of cells (64 for MK4096) is read and written back. As a result now only 128 refresh cycles are needed within 2 ms, an overhead of just 3,2% of all cycles, leaving 96.8% for data access. Or in mathematical terms, O=N is turned into O=SQR(N). An incredible reduction, isn't it?

A drawback of such a line orientated access is that it now has to work in two steps, first reading a line, next selecting the data to be outputed. Of course this can be done with an address of 12 bits 'flat' delivered via 12 address lines, the second half is not needed until the line read has been done.

So Mostek's improvement over Intel's 1103 was to turn this internal mechanic into an advantage to reduce pin count by multiplexing the address in a way, that the needed line address comes first, to be used to read the line and then the data address within the line to select whatever is to be signalled on the data out pin(s). Now DRAM could be made as small as 16 pin but still hold 4 KiBit of Data.

Most ROMs didn't break addressing into columns and rows, they just took a straight address off the address bus. So, there would be no reason for them to do this.